Advanced Micro Devices, Inc

<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN" "http://www.w3.org/TR/REC-html40/loose.dtd"><html><body> WHAT YOU DO AT AMD CHANGES EVERYTHING   At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.   Together, we advance your career.    MTS PACKAGING ENGINEER     THE ROLE:   We are looking for a candidate that can drive supplier engagement with external manufacturer/material suppliers by delivering key performance indices in terms of new product introductions, supplier manufacturing readiness, excursion-free processes, value engineering, and enabling new capabilities. AMD's environment is fast-paced, results-oriented, and built upon a legion of forward-thinking people with a passion for winning technology!     THE PERSON:   The successful candidates must be a team player with a commitment to meeting deadlines, have a drive for solutions, and have an aptitude to thrive with the ability to work in a fast-paced multitasking environment. The successful candidate should possess excellent cross-functional project management skills, conflict management skills, and strong interpersonal skills, along with effective executive presentation and communication abilities. Demonstrating strong leadership skills is essential for excelling in this role with minimal supervision, along with a strong interest in advancing within people management.     KEY RESPONSIBILITIES:   <ul><li>As part of a layout team, you will collaborate to implement high-speed/density packages.</li><li>Perform substrate breakout patterns for ASIC packages.</li><li>Optimize package pinout, incorporating system-level trade-offs of pin assignments.</li><li>Propose layout design trade-offs to the Technical Package Lead for resolution and implementation.</li><li>Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.</li><li>Develop symbols and CAD library databases using Cadence APD design tools</li><li>Develop methodologies to improve layout productivity</li><li>Requirements (technology, stack-up, etc.) in the project conception stages and negotiate with chip/system teams on product specification</li><li>Conduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (design guidelines, technology, stack-up, manufacturing time, etc.) for various device packaging using the Cadence APD or SiP tool suite. . </li><li>Collaborate with PCB Layout Engineers to optimize the package ball map and chip team to optimize the die size</li><li>Come up with performance metrics for organic package technologies in order to design high-speed chips and systems</li><li>Performing Power Integrity analysis for core as well as IO and generate power delivery network requirements with emphasis on model-to-measurement correlation</li><li>Develop scripts for checking package parameters across device families and maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations. </li></ul> PREFERRED EXPERIENCE:   <ul><li>Strong knowledge in Flip Chip Packaging (while operational experience in bumping process, substrate manufacturing, Assembly manufacturing, lid & stiffener manufacturing process is an added advantage) </li><li>Track record of development work leading to volume production in Semiconductor manufacturing </li><li>Good leadership and interpersonal skills </li><li>Have a good understanding of various Organic/PCB technologies to interpret/negotiate layout guidelines</li><li>Experience in package/PCB layout is preferred. Experience in high-power Gbps IO products is a plus.</li><li>Significant background with Cadence APD or SiP and PCB layout tools, including Constraint Manager, is a plus. Knowledge of SKILL is a plus.</li><li>Working knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD, etc.</li><li>Knowledge of DoE and DFM/DFR is a plus.</li><li>Good knowledge of SerDes design and package/PCB layout constraints</li><li>Experience using Valor is helpful </li></ul> ACADEMIC CREDENTIALS:   <ul><li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Hold a B.S. Electrical Engineering or equivalent experience.</li><li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">10+ Years of Experience in High-Speed Package/PCB Layout Design.</li></ul>  #LI-SR4 <div> </div><div> </div> Benefits offered are described:  <a href="https://amd.jibeapply.com/benefits" target="_blank" rel="noopener">AMD benefits at a glance</a>.  AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. </body></html>

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